1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to the structure of a scan driver IC to be incorporated into the liquid crystal display device.
2. Discussion of the Related Art
The cathode ray tube (CRT) is the most widely used display device in a television set or a computer monitor, because the CRT can easily reproduce full color images at a high response speed. However, the CRT is bulky, heavy, and requires a high supply of power, making portable implementations difficult. Research and development in recent years has led to display alternatives to overcome these disadvantages of the CRT. Among these alternatives is the liquid crystal display (LCD).
The LCD can be applied to a thin television set, such as those used for mounting on the wall. This is because the LCD does not employ an electron gun as the CRT does. Furthermore, the LCD can be applied to a portable display device such as a note-book computer, because the power consumption of an LCD is low enough to be driven by a battery.
As shown in FIG. 1, the LCD device includes a liquid crystal panel, a scan driver 15, and a data driver 14. The liquid crystal panel includes a matrix array of a plurality of scan lines 10 and a plurality of data lines 11. At the intersections of the scan lines 10 and data lines 11, switching elements, such as thin film transistor (TFT) 12, are formed. At a rectangular area surrounded by two neighboring scan lines and two neighboring data lines, a pixel electrode is formed to be connected to the TFT 12. The scan driver 15 applies scan signals, which are either ON or OFF signals, to the gates of the respective TFTs 12 through the scan lines sequentially. The data driver 14 applies data signals to the data lines in order to send the image data to pixel electrodes 13 through the TFTs 12 driven by the scan signal.
According to the conventional art, as shown FIG. 2, the scan driver 15 includes a plurality of odd row selectors and a plurality of even row selectors connected in series. The odd row selector includes an M2 transistor having a gate connected to an SIn terminal, to which a shift input signal is applied. The M2 transistor also has a drain connected to a first common voltage Vss1. An M1 transistor has a gate connected to an S1o terminal, to which a first clock signal is applied. The M1 transistor also has a source connected to a high voltage signal Vcc and a drain connected to the source of the M2 transistor. An M4 transistor has a gate connected to the SIn terminal and a source connected to an S2o terminal, to which a second clock signal is applied. The M3, M5 and M7 transistors each have gates connected to a node a2, which connects the drain of the M1 transistor and the source of the M2 transistor. An M6 transistor has a gate connected to the drain of the M4 transistor and a source connected to a third clock signal S3o. An M11 transistor has a gate connected to the SIn terminal and a source connected to the Vss1 common voltage. An M9 transistor has a gate connected to a fourth clock signal S4, the clock speed of which is twice that of S1o. The M9 transistor also has a source connected to the next scan line. An M10 transistor has a gate connected to the drain of the M9 transistor and a source connected to the drain of the M11 transistor. An M8 transistor has a gate connected to a node d2, which is connected to the source of the M10 transistor and the drain of the M11 transistor. The M8 transistor also has a drain connected to the source of the M7 transistor and the drain of the M6 transistor, as well as a source connected to the drain of the M7 transistor and a second common voltage Vss.
The even selector includes an M2 transistor having a gate connected to an SIn+1 terminal, to which a shift input signal is applied. The M2 transistor also has a drain connected to the first common voltage Vss1. An M1 transistor has a gate connected to an S1e terminal, to which a first clock signal is applied. The M1 transistor also has a source connected to the high signal voltage Vcc, as well as a drain connected to the source of the M2 transistor. An M4 transistor has a gate connected to the SIn+1 terminal and a source connected to an S2e terminal, to which a second clock signal is applied. The M3, M5 and M7 transistors each have gates connected to a node a3, which connects the drain of the M1 transistor and the source of the M2 transistor. An M6 transistor has a gate connected to the drain of the M4 transistor and a source connected to a third clock signal S3e. An M11 transistor has a gate connected to the SIn+1 terminal and a source connected to the common voltage Vss1. An M9 transistor has a gate connected to a fourth clock signal S4, the clock speed of which is twice that of the S1e clock signal. The M9 transistor also has a source connected to the next row (scan line). An M10 transistor has a gate connected to the drain of the M9 transistor and a source connected to the drain of the M11 transistor. An M8 transistor has a gate connected to a node d3, which connects the source of the M10 transistor and the drain of the M11 transistor. The M8 transistor also has a drain connected to the source of the M7 transistor and the drain of the M6 transistor. The M8 transistor has a source connected to the drain of the M7 transistor and the second common voltage Vss.
Here, the clock speeds of the three clock signals applied to the odd row selector, S1o, S2o, and S3o, and the three clock signals applied to the even row selector, S1e, S2e, and S3e, are half of that of the horizontal sync signal. The clock signals applied to the odd row selector have a "HIGH" pulse when the clock signals applied to the even row selector have a "LOW" pulse and vice versa. Moreover, the clock signal S4 has the same cycle as the horizontal sync signal. Because of this, the odd row selector sends the scan signal generated by the S1o, S2o, S3o, and SIn signals to the scan line connected thereto. The even row selector sends the scan signal generated by the S1e, S2e, S3e, and SIn+1 signals to the scan line connected thereto. When the nth row selector sends a scan signal to the nth scan line, the scan signal is sent to the next row selector as a shift signal. If the nth row selector is an odd row selector, the shift signal is sent to the SIn+1 terminal of the next (even) row selector. An initial shift signal is applied to the first row selector.
The operation of the scan driver will be explained with reference to circuit diagram FIG. 2 and clock signal diagram FIG. 3. Assume that the first row selector shown in FIG. 2 is an odd row selector, and the initial shift signal of a "HIGH" state for selecting the first scan line is applied to the SIn terminal at time t2. As a result, the M2 and M4 transistors are turned on at time t2. When the S1o and S2o terminals are in a "LOW" state, the sources and drains of the M2 and M4 transistors are not provided with any "HIGH" signals. In this condition, the M3, M5 and M7 transistors are not turned on. Since the source of the M4 transistor is not provided with a "HIGH" signal, the M6 transistor is not turned on.
After a "HIGH" signal is applied to SIn, if the clock signal S1o generated by the horizontal sync signal is "HIGH", then the M1 transistor is turned on at time t3 (FIG. 3). As a result, the M3, M5 and M7 transistors are all turned on. These transistors are connected to the node a2 connecting the M1 and M2 transistors. However, the M5 transistor is not supplied with a "HIGH" signal, because the M4 transistor is not provided with a "HIGH" signal (S2o is "LOW"). Moreover, the M7 transistor is not supplied with a "HIGH" voltage, because the M6 transistor is not turned on.
Before the S1o clock signal changes to "LOW", the S2o clock signal becomes "HIGH" at time t4. Then, the M6 transistor is turned on by the signal of the M4 transistor through node b2 at time t4. At that time, the S2o voltage coming through the M5 transistor reaches the M11 transistor turned on by the SIn signal and turns on the M8 transistor.
When the S1o signal becomes "LOW" at time t5, the M1 transistor is turned off and the M5 and M7 transistors, of which gates are connected to the node a2, are also turned off at time t5. While S1o is "LOW" and S2o is "HIGH", S3o becomes "HIGH" at time t6. At that time, the M6 transistor is turned on by the clock signal S2o, and the clock signal S3o is applied to the first scan line connected to the Rn terminal (signal r1 in FIG. 3).
At the same time, the S3o clock signal is applied to the SIn+1 terminal of the next (second) row selector for terminal Rn+1 as a shift signal. When the S1e of the second row selector becomes "HIGH" at time t7, the SIn becomes "LOW". At that time, the M2, M4 and M11 transistors in the first row selector are turned off and the second row selector starts working in a similar manner to the first row selector, as described above.
In manufacturing a conventional LCD device, the liquid crystal panel and the driving ICs are separately manufactured and assembled using a lead wire of lead film. In recent years, there is a need for manufacturing the driving ICs directly on the liquid crystal panel. However, the conventional structure of the driving circuit is too complicated and includes too many lead lines to allow manufacturing of the driving circuit directly on the liquid crystal panel.
Moreover, the clock signal's converting timing to a "HIGH" signal lags behind the horizontal sync signal's converting timing to a "HIGH" signal in the conventional arrangement. If the transistor used in the driving IC is formed of an amorphous silicon having a slow response time in character, a need arises to guarantee the sufficient response time for the driving IC. Consequently, it is necessary to moderate or adjust the signals used to drive the devices according to characteristics of the materials making up the driving ICs. If the driving ICs are made of polysilicon, which has a faster response time, it is difficult to precisely control the driver ICs.
Furthermore, according to the wave shape of the clock signals S1, S2, and S3, their "HIGH" states are overlapped with each other. The "HIGH" state of the S3 signal causes unpredicted influences to the shift signal. This is because most of the TFTs are simultaneously turned on when a scan line is selected. This results in a higher load in the circuit of the driving ICs.
Therefore, a manufacturing method by which a simpler scan driver IC can be integrally manufactured on the same substrate as the TFT array is desired. Applicant has a patent application number P97-00293 pending in the Korea Industry Properties Office. This Korean application has a corresponding U.S. patent application to the same inventor (Attorney docket number 043695-5019). These applications describe a scan driver composed of a plurality of row selectors, each including, as shown in FIG. 4, a D input terminal for receiving a shift signal; a CU input terminal for receiving a set signal; a CD input terminal for a reset signal; an M1 transistor having a gate connected to the CU terminal and a source connected to the D terminal; an M2 transistor having a source connected the drain of the M1 transistor; a gate connected to the CD terminal, and a drain connected to a common voltage Vss; an M3 transistor having a gate connected to the CD terminal and a source connected to a high signal voltage Vcc; an M4 transistor having a gate connected to the CU input terminal, a source connected to the drain of the M3 transistor, and a drain connected to the common voltage Vss; an M5 transistor having a gate connected to a node "a" connecting the drain of the M1 and the source of the M2, and a source connected to Vcc; an M6 transistor having a gate connected to a node "b" connecting the drain of the M3 transistor and the source of the M4 transistor, a source connected to the drain of the M5 transistor, and a drain connected to Vss; a first capacitor Ch having an electrode connected to a node "c" connecting the node "a" and the gate of the M5 transistor and another electrode connected to the common electrode Vss; a second capacitor Cs having an electrode connected to a node "d" connecting the node "b" and the gate of the M6 transistor and another electrode connected to the common voltage Vss; and an output terminal R connected to a node "e" connecting the drain of the M5 transistor and the source of the M6 transistor.
The scan driving IC includes a plurality of the row selectors described above serially connected. The output terminal R is connected to the D terminal of the next row selector, as shown in FIG. 5. The odd row selectors are provided with set signals from the CK1 clock signal, and reset signals from the CK2 clock signal. The even row selectors are provided with the set signals from the CK3 clock signal and the reset signals from the CK4 clock signal. The input terminal for the shift signal of the first row selector is supplied with a start pulse CKs.
The waveforms of the CK1, CK2, CK3, and CK4 signals have the same cycle, as shown in FIG. 6, and follow a rule as follows. After the CK1 signal has pulsed once and before the CK1 rises to a "HIGH" level again, the CK2 signal has one pulse. After the CK1 signal goes from "HIGH" to "LOW" and before the CK2 becomes "HIGH" again, the CK3 has one pulse. After the CK3 goes from "HIGH" to "LOW" and before the CK3 becomes "HIGH" again, the CK4 has one pulse.
Referring to the structure of the driving IC, shown in FIGS. 4 and 5 and the waveforms of FIG. 6, operation of this scan driving IC will be described. At the first row selector, during the ON ("HIGH") signal of the CKs applied to the shift terminal, the M1 and M4 transistors are turned on because of the ON ("HIGH") signal from the CK1 clock signal. When the M2 transistor is not turned on, the CKs signal is sent to the gate of the M5 transistor through the node "a". Therefore the M5 transistor is turned on. The CKs signal ("HIGH")is also stored at the capacitor Ch located between the gate of the M5 and the node "a". At this point, the M6 transistor is not turned on. Thus, Vcc is applied to the Ro terminal through the M5 transistor. Hence, the first scan line R1 is selected.
When the CK1 becomes "LOW", the M1 transistor is turned off. Then, the Ch capacitor is no longer supplied with a "HIGH" signal and the Ch capacitor begins discharging. However, the M1 and the M2 transistors are turned off, and thus the discharged signal is supplied to the gate of the M5 transistor. Therefore, the M5 transistor is still being turned on and a "HIGH" signal is applied to the Ro terminal in spite of the CK1 signal being "LOW".
The CK3 signal becomes "HIGH" before the CK2 signal becomes "HIGH". At that time, the output terminal Ro of the first row selector has a "HIGH" signal and the "HIGH" signal is applied to the De terminal of the second row selector. The source of the M1 transistor of the second selector, which is turned on by the CK3 signal, is provided with the "HIGH" signal of the Ro terminal, and accordingly, the M5 transistor of the second selector is turned on. Thus, a "HIGH" signal is applied to the Re terminal of the second row selector. This results in the second scan line R2 being selected. That is, the Ro terminal of the first row selector provides the shift signal to the De terminal of the second row selector while the CK3 signal is in a "HIGH" state. Similarly, the "HIGH" signal of the Re terminal of the second row selector is a shift signal of the Do terminal of the third row selector. Even when the CK3 signal is "LOW", the stored shift signal at the capacitor Ch of the second selector turns on the M5 transistor. Thus, the Re terminal of the second row selector remains in the "HIGH" state.
The CK2 signal becomes "HIGH" after the CK3 signal becomes "LOW". At that time, the M2 transistor and the M3 transistor of the first row selector are turned on. Thus, the discharging signal voltage from the capacitor Ch is no longer applied to the gate of the M5 transistor of the first row selector and, the M5 transistor of the first row selector is turned off. At the same time, in the first row selector, the Vcc is applied to the gate of the M6 transistor and to the Cs capacitor through the M3 transistor. As a result, the M6 transistor is turned on and the common voltage Vss is applied to the output terminal Ro. Therefore, the Ro terminal of the first row selector becomes "LOW". That is, the first scan line R1 is unselected. The M6 transistor is still turned on even when the CK2 signal becomes "LOW", because the M2 and the M3 transistors are turned off and the "HIGH" signal stored at the Cs capacitor is discharged to the gate of the M6 transistor of the first row selector.
The second "HIGH" level of the CK1 signal is applied before the CK4 signal is "HIGH". At that time, the "HIGH" signal of the Re terminal of the second row selector is applied to the Do terminal of the third row selector. As a result, the M1 transistor of the third row selector is turned on by the "HIGH" level of the CK1 signal, and the M5 transistor is turned on by the "HIGH" level of the Do terminal through the M1 transistor. Therefore, the "HIGH" signal is supplied to the Ro terminal of the third row selector. That is, the third scan line is selected. The "HIGH" signal of the Re terminal of the second row selector is a shift signal of the third row selector while the CK1 signal is in a "HIGH" state. Similarly, the "HIGH" signal of the Ro terminal of the third row selector is a shift signal for the fourth row selector, while the CK3 signal is in a "HIGH" state.
The CK4 signal is "HIGH" after the CK1 signal is "LOW". At that time, the M2 and M3 transistors of the second row selector are turned on. As a result, the discharging voltage from the Ch capacitor passes through the M2 transistor, not being applied to the gate of the M5 transistor. Therefore, the M5 transistor is turned off. At the same time, the M6 transistor is turned on, because the Vcc is applied to the M6 transistor and the Cs capacitor through the M3 transistor. As a result, the common voltage Vss is applied to the Re terminal of the second row selector. That is, the second scan line is unselected. When the CK4 signal becomes "LOW", the M6 transistor is still turned on, because the M2 and M3 transistors are turned off and the stored voltage at the Cs capacitor is applied to the gate of the M6 transistor of the second row selector. Therefore, the Re terminal of the second row selector maintains its "LOW" state.
In this embodiment of the applicant's invention above, the high state of the scan selection signal of one row selector overlaps the high state of the scan selection signal of the next row selector, as in the case of the conventional driving Ics, as shown in FIGS. 3 and 6. This results in a problem in applying the data voltage to the pixel electrode. This LCD incorporated with a scan driver IC should utilize an inversion method, such as the dot inversion method or the line inversion method. However, the driving signal of a row selector is overlapped with the shift signal of the next row selector. As a result, the scan selection signal of a row selector is applied to the next row. Therefore, the pixels connected to the next row are applied with an excess voltage during the overlapping period, so the pixels receive electrical stresses. In order to solve this problem, a frame inversion method may be adapted. However, the frame inversion method results in a lower quality display than the dot or line inversion method as a result of cross talk or flicker.